Chisel 2 mod for minecraft 1.16.5/1.12.2/1.11.2

Getting Started

Build Your Own Chisel Projects

See the setup instructions for how to set up your environment to build Chisel locally.

When you’re ready to build your own circuits in Chisel, we recommend starting from the Chisel Template repository, which provides a pre-configured project, example design, and testbench.
Follow the chisel-template README to get started.

If you insist on setting up your own project from scratch, your project needs to depend on both the chisel3-plugin (Scalac plugin) and the chisel3 library.
For example, in SBT this could be expressed as:

// build.sbt
scalaVersion = "2.12.13"
addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.4.4" cross CrossVersion.full)
libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.4.4"
scalacOptions += "-Xsource:2.11"
// We also recommend using chiseltest for writing unit tests 
libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "0.3.4" % "test"

Design Verification

These simulation-based verification tools are available for Chisel:

• iotesters, specifically PeekPokeTester, provides constructs (, , ) similar to a non-synthesizable Verilog testbench.
• testers2 is an in-development replacement for PeekPokeTester, providing the same base constructs but with a streamlined interface and concurrency support with and .

Glitches

There is a glitch in Chisel 2 that some enemies will rapidly bang into each other.

The glitch in action

If the player drills in a particular matter on level 5, one half of the moon will disappear.

Infinite Drilling glitch

If the player drills through a small planet (no matter the level) enough times to make it as small and drillable as possible, the player can glitch and cause Chiseler to drill through the planet and possibly throughout the void of space for the rest of his robotic life.

The glitch in action.

Level skip

If a level is completed quickly, and the button next is clicked, on the start of the level a box will pop up saying level complete. If the level section is visited again, the skipped level will have a lock on it.

The level section after the level skip glitch has been done

Level failed glitch

Like the level skip glitch, if the level has been failed quickly, and the replay button is clicked, a box will pop up at the start of the level saying it has been failed.

Sound FX glitch

If the player mutes the sound FX while they are drilling the sound of them drilling will not stop until they drill again with the sound FX not muted.

Barricadebot glitch

If the player starts a level in which Chiseler spawns right above a Barricadebot and the player presses the drill button at the right frame, he/she will be able to drill right through the Barricadebot. Rapidly pressing the space bar right as the screen transition starts will make this glitch easy to perform.

The player clipping through a Barricadebot right at the beginning of level 16

What does Chisel code look like?

Consider an FIR filter that implements a convolution operation, as depicted in this block diagram:

While Chisel provides similar base primitives as synthesizable Verilog, and could be used as such:

// 3-point moving sum implemented in the style of a FIR filter
class MovingSum3(bitWidth: Int) extends Module {
  val io = IO(new Bundle {
    val in = Input(UInt(bitWidth.W))
    val out = Output(UInt(bitWidth.W))
  })

  val z1 = RegNext(io.in)
  val z2 = RegNext(z1)

  io.out = (io.in * 1.U) + (z1 * 1.U) + (z2 * 1.U)
}

the power of Chisel comes from the ability to create generators, such as an FIR filter that is defined by the list of coefficients:

// Generalized FIR filter parameterized by the convolution coefficients
class FirFilter(bitWidth: Int, coeffs: Seq) extends Module {
  val io = IO(new Bundle {
    val in = Input(UInt(bitWidth.W))
    val out = Output(UInt(bitWidth.W))
  })
  // Create the serial-in, parallel-out shift register
  val zs = Reg(Vec(coeffs.length, UInt(bitWidth.W)))
  zs() = io.in
  for (i <- 1 until coeffs.length) {
    zs(i) = zs(i-1)
  }

  // Do the multiplies
  val products = VecInit.tabulate(coeffs.length)(i => zs(i) * coeffs(i))

  // Sum up the products
  io.out = products.reduce(_ + _)
}

and use and re-use them across designs:

val movingSum3Filter = Module(new FirFilter(8, Seq(1.U, 1.U, 1.U)))  // same 3-point moving sum filter as before
val delayFilter = Module(new FirFilter(8, Seq(.U, 1.U)))  // 1-cycle delay as a FIR filter
val triangleFilter = Module(new FirFilter(8, Seq(1.U, 2.U, 3.U, 2.U, 1.U)))  // 5-point FIR filter with a triangle impulse response

The above can be converted to Verilog using :

import chisel3.stage.{ChiselStage, ChiselGeneratorAnnotation}

(new chisel3.stage.ChiselStage).execute(
  Array("-X", "verilog"),
  Seq(ChiselGeneratorAnnotation(() => new FirFilter(8, Seq(1.U, 1.U, 1.U)))))

Alternatively, you may generate some Verilog directly for inspection:

val verilogString = (new chisel3.stage.ChiselStage).emitVerilog(new FirFilter(8, Seq(.U, 1.U)))
println(verilogString)

Upcoming Events

Chisel Dev Meeting

Chisel/FIRRTL development meetings happen every Monday and Tuesday from 1100–1200 PT.

Call-in info and meeting notes are available here.

Chisel Community Conference 2021, Shanghai, China.

CCC is an annual gathering of Chisel community enthusiasts and technical exchange workshop.
This year with the support of the Chisel development community and RISC-V World Conference China 2021 Committee, we have brought together designers and developers with hands-on experience in Chisel from home and abroad to share cutting-edge results and experiences from both the open source community as well as industry.
English translated recordings version will be updated soon.
Looking forward to CCC 2022! See you then!

Chisel is a hardware design language that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs.
Chisel adds hardware construction primitives to the Scala programming language, providing designers with the power of a modern programming language to write complex, parameterizable circuit generators that produce synthesizable Verilog.
This generator methodology enables the creation of re-usable components and libraries, such as the FIFO queue and arbiters in the , raising the level of abstraction in design while retaining fine-grained control.

For more information on the benefits of Chisel see: “What benefits does Chisel offer over classic Hardware Description Languages?”

Chisel is powered by FIRRTL (Flexible Intermediate Representation for RTL), a hardware compiler framework that performs optimizations of Chisel-generated circuits and supports custom user-defined circuit transformations.

Инструменты

Битовый мешок

• Автоматически сохраняет части блоков (биты), которые вы удаляете и используете.
• Может содержать до 63-битных стеков.
• Суммируется до 512 бит вместо 64 как в обычном инвентаре.
• Имеет кнопку, позволяющую стереть содержимое сумки.
• Перетащите стопку битов на кнопку «Удалить», чтобы удалить только ненужные биты. (только для версий 11.4 / 10.12 и выше)

• Разрезает симметричные блоки пополам.
• Быстро и легко нарезает блоки на плиты, панели или другие кубические формы.

Крафт пилы

Битовый бак

Преобразует резервуары для жидкости в долота для жидкости и наоборот

Щелкните правой кнопкой мыши ведром: это добавит биты жидкости.
Щелкните правой кнопкой мыши: извлеките биты жидкости
Shift + щелкните правой кнопкой мыши: вставьте биты жидкости
Рецепт

Алмазное, золотое, железное и каменное долото

• Алмаз:  долото с большим количеством использований.
• Золото:  самые бесполезные инструменты из этого материала ломаются еще до того, как вы начнете работу.
• Железо:  Долото среднего качества.
• Камень:  Обычное долото, имеет очень ограниченное применение.

• — Может долбить до 194 полных блоков.
• — Позволяет удалять биты из блоков.
• — Имеет различные режимы вырезания, однобитовый, линейный, плоский и многое другое.
• — Может обрабатывать любой материал, разбить который можно только алмазной киркой.

• — Может долбить до четверти блока.
• — Позволяет удалять биты из блоков.
• — Имеет разные режимы, одиночный бит, линия, плоскость и многое другое.
• — Может собирать любой материал, для которого требуется золотая кирка.

• — По умолчанию может обработать до 71 целого блока.
• — Позволяет удалять биты из блоков.
• — Имеет разные режимы, одиночный бит, линия, плоскость и многое другое.
• — Может собирать любой материал, для которого требуется железная кирка.

• — Можно обработать до 2-х полных блоков.
• — Позволяет удалять биты из блоков.
• — Имеет разные режимы, одиночный бит, линия, плоскость и многое другое.
• — Может собирать любой материал, для которого требуется каменная кирка.

Рецепты

• Клонирование блоков.
• Можно использовать для создания копий на верстаке.
• Можно стирать и использовать повторно.
• Имеет 4 режима работы. (Версия 11.4 / 10.12 и выше)
• Замена: классический режим, целевой блок заменяется дизайном.
• Добавка: добавляет только те части, в которые они входят.
• Impose: добавляет и заменяет биты, но не удаляет их.
• Размещение: разместите выкройку, как если бы это был точеный блок.

• Передает формы между материалами
• Можно перевернуть в верстаке.
• Можно стирать и использовать повторно.

• Обратить биты по определенной оси.
• Может быть преобразован в положительную или отрицательную конструкцию долота.
• Можно стирать и использовать повторно.

Рецепт

• Измеряйте расстояния, используя 3 режима.
• Битовый режим: измерение расстояний до битовых уровней в виде трехмерного куба.
• Режим блока: измерение расстояний на уровне блока в виде трехмерного куба.
• Режим расстояния: измерение расстояния от начальной до конечной точки на битовом уровне.

Рецепт
мода

Upcoming Events

Chisel Community Conference 2021, Shanghai, China.

CCC is an annual gathering of Chisel community enthusiasts and technical exchange workshop.
This year with the support of the Chisel development community and RISC-V World Conference China 2021 Committee, we have brought together designers and developers with hands-on experience in Chisel from home and abroad to share cutting-edge results and experiences from both the open source community as well as industry.
English translated recordings version will be updated soon.
Looking forward to CCC 2022! See you then!

Chisel is powered by FIRRTL (Flexible Intermediate Representation for RTL), a hardware compiler framework that performs optimizations of Chisel-generated circuits and supports custom user-defined circuit transformations.

Trivia

• Chisel 2 takes place in a galaxy which was supposed to be destroyed by Chiseler (according to the prequel’s end).
• Foreman Buzz breaks the fourth wall in the first level by mentioning the «last game» (Chisel 1).
• Scratchbots and bomb crabs are accidentally called digbots and boombots in Chisel 2, respectively. Both of their re-given names are actually names of enemies in Chisel 1.
• Sprites of the wormholes and red field of the player’s bombs of Nanobots exist in the coding, but are unused.
• In level 4, when Chiseler says, «My sensors indicate (this asteroid field) hasn’t been used since 1979.», it is shown that the level design is the same of the Atari game Asteroids, which was released in 1979.
• For the Nitrome Jam game Rockitty: 9 Lives, there is an icon for Chisel in the «More projects created by this team members» section credited as Chisel but leading to Chisel 2.

The icon

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Getting Started

Bootcamp Interactive Tutorial

The online Chisel Bootcamp is the recommended way to get started with and learn Chisel.
No setup is required (it runs in the browser), nor does it assume any prior knowledge of Scala.

The classic Chisel tutorial contains small exercises and runs on your computer.

A Textbook on Chisel

If you like a textbook to learn Chisel and also a bit of digital design in general, you may be interested in reading Digital Design with Chisel. It is available in English, Chinese, Japanese, and Vietnamese.

Build Your Own Chisel Projects

See the setup instructions for how to set up your environment to build Chisel locally.

When you’re ready to build your own circuits in Chisel, we recommend starting from the Chisel Template repository, which provides a pre-configured project, example design, and testbench. Follow the chisel-template readme to get started.

If you insist on setting up your own project, the magic SBT lines are:

Design Verification

These simulation-based verification tools are available for Chisel:

• iotesters, specifically PeekPokeTester, provides constructs (, , ) similar to a non-synthesizable Verilog testbench.
• testers2 is an in-development replacement for PeekPokeTester, providing the same base constructs but with a streamlined interface and concurrency support with and .